An electroabsorption modulator (EAM) is a photonic semiconductor device that allows the intensity of a laser beam traveling through it to be controlled via an electric voltage. The principle of operation of the modulator is based on applying an electric field to cause a shift of the material absorption threshold toward longer wavelengths. A laser beam with a wavelength longer than that of the absorption threshold will either be transmitted without applied electric field or absorbed by applied electric field. A typical EAM has a waveguide structure and electrodes for applying an electric field in a direction that is perpendicular to the modulated light beam. In order to achieve a high extinction ratio, EAMs typically include a quantum well structure in the core of the waveguide. Due to the Quantum-Confined Stark Effect (QCSE), the quantum-well structure provides a strong shift of the absorption threshold at low electric fields. EAMs based on QCSE are capable of operating at relatively low voltages and at very high speeds (e.g., gigahertz (GHz)), which makes them suitable for use in optical communications systems.
A distributed feedback laser (DFB) is a laser in which the entire cavity is made up of a periodic refractive-index structure that functions as a distributed reflector at the lasing wavelength, and contains a gain medium. An EAM can be monolithically integrated with a DFB on a single chip to form an electroabsorption modulated distributed feedback laser (EML) device that is capable of operating as a data transmitter. EML devices have been proposed that operate at high data rates (e.g., 10 gigabit per second (Gb/s)) in the 1550 nanometer (nm) and 1310 nm ranges. There are many difficulties that must be overcome in order to manufacture large volumes of these devices with high yield.
FIG. 1 illustrates a cross-sectional top view of a known EML device 2 comprising a DFB 3 and an EAM 4. The DFB 3 and the EAM 4 each have metallic contact pads 5 and 6, respectively. One end facet 7 of the EML device 2 comprises a highly-reflective (HR) or anti-reflective (AR) coating. The other end facet 8 of the EML device 2 comprises an AR coating. An inter-contact isolation region 9 electrically isolates the DFB 3 and the EAM 4 from each other. The lines labeled 11A and 11B represent a straight reverse-mesa ridge structure 11 that extends across the DFB 3, the isolation region 9, and the EAM 4. The lines 13A and 13B delineate the channels located on either side of the ridge waveguide structure 11, which are created when the ridge waveguide structure 11 is formed.
The EML device 2 has trenches 12A and 12B formed therein to remove defect areas that exist after a surface area growth (SAG) process has been used to grow a multiple quantum well (MQW) structure, as described below in more detail with reference to FIG. 2A. The trenches 12A and 12B are generally uniform in width through the DFB 3, the EAM 4, and the isolation region 9. The trenches 12A and 12B are generally in parallel with and run alongside the reverse-mesa ridge structure 11.
FIG. 2A illustrates a cross-sectional view of the EML device 2 shown in FIG. 1 along the A-A′ cross-section shown in FIG. 1. The different semiconductor layers that make up the EML device 2 are as follows. An n-type (001) Indium Phosphide (InP) material 21 is used as the substrate for the assembly 2. The substrate 21 has an n-type InP buffer layer 22 formed thereon. A MQW active region 23 is grown on top of the buffer layer 22 by a process known as Selective Area Growth (SAG). A p-type InP spacer layer 25 is grown on top of the MQW layer 23. A p-type Indium Gallium Arsenide Phosphide (InGaAsP) etch-stop layer 26 is grown on top of the spacer layer 25. Another p-type InP spacer layer 27 is grown on top of the InGaAsP etch-stop layer 26. A p-type InGaAsP grating layer 28 is grown on top of the spacer layer 27. A grating layer 28 is selectively etched in the DFB portion 3 to form a periodically varying refractive index region 31, which provides a filter for the laser spectrum in a desired wavelength value. A p-type InP infill 29 and cladding layer 32 are re-grown on top of layer 28. A p-type InGaAs contact layer 33 is then grown on top of the cladding layer 32.
FIG. 2B illustrates a cross-sectional view of the DFB portion 3 of the EML device 2 along the E-E′ cross-section shown in FIG. 2A. After the contact layer 33 is grown, a silicon oxide (SiO2) dielectric mask 34 represented by mask portions 34A, 34B and 34C is deposited on the top of the contact layer 33 and a wet chemical etch process is performed to etch the contact layer 33 and the cladding and infill layers 32 and 29.
FIG. 3 illustrates an enlarged view of the DFB portion 3 of the EML device 2 along the E-E′ cross-section shown in FIG. 2A after the chemical etching process has been performed. When the chemical etch process is performed, the device 2 etches relatively quickly in the (001) plane, but relatively slowly in the (111) plane, causing the waveguide ridge 35 to be formed with lateral (111) facets 36 thereon, having an angle, co, between the (001) and (111) facets that is typically about 54.7 degrees. This ridge configuration is commonly referred to as a reverse-mesa ridge configuration due to the fact that the top of the ridge is wider than the base of the ridge.
FIG. 4A illustrates a cross-sectional view of the DFB 3 shown in FIG. 2A along the E-E′ cross-section prior to the layers of the MQW active region being grown using the SAG process. Prior to performing the SAG process to grow the MQW active region, a dielectric mask pattern comprising a plurality of rectangular mask portions 54A and 54B are deposited on top of the substrate 21, leaving openings 22 in which to grow the MQW active region.
FIG. 4B illustrates a cross-sectional view of the DFB 3 along the E-E′ cross-section shown in FIG. 2A after the layers making up the MQW active region 23 have been grown. The layers 23 are grown only on the areas of the surface of the substrate 21 that are exposed through the mask pattern 54A and 54B.
FIG. 4C illustrates a cross-sectional view of the EAM 2 along the E-E′ cross-section shown in FIG. 2A after the mask pattern 54A and 54B has been removed. After the mask pattern 54 has been removed, it can be seen that the surface is essentially non-planar. This non-planar surface is difficult to work with in performing the additional processes described above with reference to FIGS. 2A and 2B, e.g., growing the p-type InP spacer layer 25 on top of the MQW layer 23, growing the p-type InGaAsP etch-stop layer 26 on top of the spacer layer 25, growing the p-type InP spacer layer 27 on top of the InGaAsP etch-stop layer 26, growing the p-type InGaAsP grating layer 28 on top of the spacer layer 27, forming the periodically varying refractive index region 31 in the grating layer 28, etc., up through and including the formation of the reverse-mesa ridge structure 35. Because of the difficulties of working with the non-planar surface that results after the SAG process has been performed, the resulting assemblies may have performance problems, which will typically result in reduced manufacturing yield and increased costs.
With reference again to FIG. 1, it is important for the isolation region 9 between the DFB 3 and the EAM 4 to have high resistance and low capacitance. One technique that is used to provide the isolation region 9 with high resistance is to perform ion implantation in order to implant ions in the isolation region 9 to increase its resistance. One disadvantage of this technique is that it increases process complexity, which increases costs. Another disadvantage of this technique is that it is not always effective at providing the isolation region 9 with a sufficiently high resistance, which can lead to performance problems, and consequently, to reduced yield and increased costs.
A technique that is sometimes used to provide the isolation region 9 with decreased capacitance involves depositing a thick dielectric material underneath the contact pads 5 and 6. One disadvantage of this technique is that it increases process complexity, which increases costs. Another disadvantage of this technique is that it sometimes results in the contact pads 5 and 6 failing to adhere to the EML device 2. In other words, the pads 5 and 6 can peel away from the assembly 2, resulting in performance problems, and consequently, in reduced yield and increased costs.
Accordingly, a need exists for a photonic semiconductor device, such as an EML device of the type described above, for example, that is capable of operating at high speeds (e.g., 10 GB/s) over a wide temperature range in the 1310 and 1550 nm windows. A need also exists for a method for manufacturing such a device in such a way that manufacturing yield is kept relatively high and costs are kept relatively low.